1. Field of Invention
The present invention relates in general to semiconductor memories. Those memories can be standalone, embedded, or stacked as multiple chips (homogeneous and heterogeneous—namely, in a memory stack, all of them can be of one kind; or, they can be different in function, utility, form factor as well as to technology).
2. Background of Invention
Semiconductor memories include dynamic random access memories (DRAM's) static random access memories (SRAM's), flash, ferroelectric, magnetic, plastic, MIM (metal-insulator-metal) RAMs, calcogenide and plastic memories, and others. The prevalent monolithic and embedded memory architecture, is multi-bank. The input/output data architecture includes double data rate (DDR), quad data rate (QDR) zero bus turnaround (ZBT SRAM's) and others. Memory storage cell architecture in nonvolatile memories, specifically flash, could be NOR or NAND (others are possible as well). As an example a conceptual block diagram of a commercially available Infineon RLDRAM (reduced latency DRAM) is shown in FIG. 1.
With the advent of diverse applications for both volatile and nonvolatile memories, a need has arisen to further enhance bandwidth and bus utilization. In peer-to peer system, as well as bus oriented systems, a need has arisen to access multiple banks/simultaneously blocks/sectors/sub-arrays, for maximum data throughput. Spin-wheel SDRAM implementations are another example of systems to address these needs. One specific application where data moves in packets (both fixed length and variable length packets) is, in communications. ATM, IP, SONET, Ethernet are some of the protocols used in communicating the information as digital data. The memory buffers used in such communications have to be flexible enough in configurability to accommodate varying length packets, with maximum efficiency (and not waste memory space). Because of the criticality of packet transmission and reception in a predetermined QOS (quality of service) deadline, each packet must be distributed across multiple banks in multiple IC's, in both INGRESS (WRITE) and EGRESS (READ) of those packets. Multiple data path memories can handle these time critical decisions without ‘loss of packets,’ which is not possible with current memory, architectures.